1. Field of the Invention
The present invention relates to a semiconductor device, which may be used as, for example, a semiconductor rectifying element having low reverse breakdown voltage such as a voltage regulator diode (Zener diode), and a manufacturing method thereof.
2. Description of the Related Art
A semiconductor diode 1 such as the voltage regulator diode shown in FIG. 1 is known. This semiconductor diode 1 may have, for example, a simple three-layer structure embracing an n-type semiconductor region 2 having a high impurity concentration, an n-type semiconductor region 3 having predetermined specific impurity concentration, and a p-type semiconductor region 4 having a high impurity concentration. In addition, on the top surface of n-type semiconductor region 2 and the bottom surface of p-type semiconductor region 4, there may be formed metal films 5, 6, which serve as the respective electrodes thereof.
Typically, with a semiconductor diode having such a stacked structure, there exists a strong electric field in the depletion layer of a p-n junction to which a reverse bias voltage is applied; however, at the chip sidewall, whereat the terminal portion of the p-n junction is exposed, it may be influenced by the impurities, ions, or the like adhered to the surface, and the electric field may become even stronger in places making it easier for breakdowns to occur. As a result, with the semiconductor diode, it becomes difficult to obtain a reverse breakdown voltage that is theoretically expected. Therefore, in order to reduce the electric field at the chip sidewall 7 of the semiconductor diode 1 as shown in FIG. 1, the chip sidewall 7 exposing the terminal portions of the p-n junction is cut so as to form the necessary angle with the p-n junction interface 9 employing a beveled structure, which is made to reduce the electric field. By employing such beveled structure, the electric field at the chip sidewall 7 may be decreased and breakdowns made to occur throughout the entirety of the junction interface, resulting in stabilization of the device performance, achieving the constant breakdown voltage. It may be noted that, as is well known, by employing a beveled structure in a power semiconductor device having higher breakdown voltage than the voltage regulator diode, the breakdown voltage can be improved.
Nevertheless, as described in the following, there are problems with the semiconductor diode 1 shown in FIG. 1.
(1) With the semiconductor diode 1 shown in FIG. 1, during the assembling process, after the chip sidewall 7 is subjected to a wet cleansing process using an acidic or alkaline chemical to protect them from the external environment, the chip sidewall 7 is covered with an insulating layer 8. However, product evaluation testing results for the semiconductor diode 1 manufactured in this manner indicated points where the performances and quality of the product were not stabilized. The changes in the surface state and surface damage to the chip sidewall 7 imparted by the wet cleansing and the covering thereof by the insulating layer 8 were given as the reasons for the poor performances, and so on, not being stabilized. Since the surface state of an actual semiconductor chip is extremely active, it is extremely difficult to control the precision and reproducibility of such surface state.
(2) In the semiconductor diode 1 shown in FIG. 1, the breakdown voltage is determined by the impurity concentration in the n-type semiconductor region 3 at the p-n junction between the n-type semiconductor region 3 and the p-type semiconductor region 4. However, in order to determine this breakdown voltage, the resistivity xcfx81 of the semiconductor wafer (silicon wafer) used in manufacturing process needs to be controlled with great precision. As a result, it becomes necessary to specially order a custom-made semiconductor wafer having a strictly defined resistivity xcfx81 from a semiconductor wafer manufacturer, and carefully test it after delivery as well. Therefore, a problem lies in the semiconductor wafer being costly. As an example, silicon wafers having a resistivity within the narrow range of 0.01 to 0.03 xcexa9xc2x7cmxe2x80x94which corresponds to the impurity concentration range of approximately 5xc3x971018/cm3 to 7xc3x971017/cm3 with the n-type siliconxe2x80x94have been conventionally custom-ordered.
(3) When manufacturing the semiconductor diode 1 shown in FIG. 1, in order to have a beveled structure by forming the chip sidewall 7 at a slant angle relative to the p-n junction plane, a problem lies in the manufacturing processes increasing in number due to the addition of various processes such as sandblasting, grinding, polishing or etching.
(4) In the assembling process of the semiconductor diode 1 shown in FIG. 1, chips cut from a semiconductor wafer are scheduled to be packaged. However, since the chip sidewalls of the respective chips are at the slant angle relative to the top/bottom surfaces of the chips, it requires much effort to load the respective chips onto jigs, such as the collets.
The present invention has come about in order to solve the above problems. Therefore, an object of the present invention is to provide a semiconductor device preventing the development of localized breakdown at the chip sidewall exposing a p-n junction, obtaining a stabilized, desired breakdown voltage.
Another object of the present invention, is to provide a semiconductor device and manufacturing method thereof, which allows for a reduction in cost of the semiconductor wafer and allows for the range of allowable resistivity xcfx81 of the semiconductor wafer used to be widened.
Still another object of the present invention is to provide a semiconductor device manufacturing method, which allows chip surface passivation processing to be simplified or to be abbreviated.
Still another object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which allows the manufacturing process to be simplified.
Yet still another object of the present invention is to provide a semiconductor device allowing for favorable handling and favorable loading of the chip into a jig, such as the collet, during the product assembly process.
In order to solve the aforementioned problems, a first aspect of the present invention inheres in a semiconductor device encompassing (a) a first semiconductor region of a first conductivity-type including a first end surface, a second end surface opposite the first end surface and a first outer surface connecting the first and second end surfaces; (b) a second semiconductor region of the first conductivity-type having a third end surface, a fourth end surface opposite the third end surface and a second outer surface connecting the third and fourth end surfaces, wherein the fourth end surface is in contact with the first end surface; (c) a third semiconductor region of a second conductivity-type, which is in contact with the first semiconductor region at the second end surface; and (d) fourth semiconductor region having an inner surface in contact with the first and second outer surfaces and an impurity concentration lower than the first semiconductor region, which is in contact with the third semiconductor region. Here the second conductivity type is the opposite conductivity type as the first conductivity type. More specifically, if the first conductivity type is assigned to be n-type, then the second conductivity type is p-type; and if the first conductivity type is assigned to be p-type, then the second conductivity type is n-type. The first conductivity type or the second conductivity type may further be an intrinsic semiconductor. For example, two p-n junction interfaces may be implemented by bringing both a high impurity concentration n-type first semiconductor region and relatively low impurity concentration n-type fourth semiconductor region into contact with a p-type third semiconductor region. Alternatively, a high impurity concentration p-type first semiconductor region and a relatively low impurity concentration p-type fourth semiconductor region may be brought into contact with an n-type third semiconductor region to provide two p-n junction interfaces is also allowable. In the case where the fourth semiconductor region is the second conductivity type, the p-n junction interface forms the boundary of the second semiconductor region and the fourth semiconductor region. In addition, the first and second outer surfaces may each respectively be a curved surface including one, two, or more certain radii of curvature.
The semiconductor device according to the first aspect of the present invention makes it easier for a breakdown to occur in the p-n junction between the first semiconductor region and the third semiconductor region than in the p-n junction between the fourth semiconductor region and the third semiconductor region positioned at the outer edge side of the semiconductor device (semiconductor chip). As a result, the electric field at the sidewall (chip sidewall) of the semiconductor device is reduced, and a breakdown is made to occur in the junction interface within the semiconductor device to allow stabilization in the prescription of the breakdown voltage. This manner of measured stabilization in the breakdown voltage is, for example, more effective in a power semiconductor device having a higher breakdown voltage than in a voltage regulator diode.
In the semiconductor device according to the first aspect of the present invention, it is preferable for the fourth semiconductor region to be a semiconductor substrate cut from bulk crystal. By adjusting the impurity concentration of the first semiconductor region, the electrical characteristics of the semiconductor device can be controlled making it so that the impurity concentration of the fourth semiconductor region does not influence the electrical characteristics of the semiconductor device. As a result, it is possible to use the fourth semiconductor region with the doping specifications of the wafer (semiconductor substrate) as it is when it is cut from the bulk crystal at the time of purchase. Namely, there is no longer any need to strictly set the doping specifications of the semiconductor substrate and it is possible to widen the range from which the semiconductor substrate (wafer) to be used may be chosen.
In the semiconductor device according to the first aspect of the present invention, the outer surfaces of the fourth semiconductor region serves as the chip outer-surface of the semiconductor device, and it is preferable that the chip outer-surface be substantially orthogonal with the second end surface of the first semiconductor region. In the case where the fourth semiconductor region has a first conductivity type, the outside p-n junction interface is exposed at the chip outer surface. However, since the breakdown at the p-n junction occurs earlier in the central portion than at the edge portion, even if there are some changes in the surface state or surface damage occurs in the outer surfaces of the semiconductor device, it is possible to suppress variations in the breakdown voltage of the semiconductor device occur. In particular, the breakdown of the p-n junction exposed at the edge portion of the chip (the chip outer surface) is dependent on the passivation architecture of the chip outer surface and xe2x80x9cvariationsxe2x80x9d in the breakdown voltage at the edge portion of the earlier chip was large. However, with the semiconductor device according to the first aspect of the present invention, since the breakdown occurs earlier in the central portion than the chip outer surface, even if there are some changes in the surface state or surface damage occurring at the edge portion of the semiconductor device (chip), it is possible to suppress fluctuations in the breakdown voltage of the semiconductor device. Accordingly, variations in the product performance are reduced, and manufacturing process yield is improved.
In the case where the fourth semiconductor region has the second conductivity type, the outside p-n junction interface is formed at the boundary of the second semiconductor region and the fourth semiconductor region, and the outside p-n junction interface is not exposed at the chip outer surface. More specifically, in this case, since the outside p-n junction interface is formed on the top surface-side of the chip, it does not come under the influence of changes in the surface conditions of the chip outer surface or surface damage. In particular, since the p-n junction is not exposed at the edge portion (chip outer surface) of the chip, there is no detailed and complicated passivation architecture required for the chip outer surface.
Moreover, since the chip outer-surface is made substantially orthogonal with the first end surface of the first semiconductor region, it is possible to form sidewall of the semiconductor device with a typical cutting process (dicing process). xe2x80x9cSubstantially orthogonalxe2x80x9d means within the range of variations of angle developing during a typical cutting process (dicing process), and intentionally means that beveling is not performed. For example, if an 80xc2x0 to 100xc2x0 angle is formed, this can be seen as being substantially orthogonal (=90xc2x0). It is preferable that an 87xc2x0 to 93xc2x0 angle be formed. If the chip outer-surface is substantially orthogonal with the edge surfaces, the handling of the semiconductor device (chip) during a fabrication (assembly) process using a jig, such as the collet, is improved.
In the first aspect of the present invention, it is preferable that a first main electrode layer be formed at the bottom surface of the third semiconductor region, and a second main electrode layer be formed at the top surface of the second semiconductor region. With the first main electrode layer and the second main electrode layer, the operational region (the main body portion), which is the main current path of the semiconductor element, is identified. xe2x80x9cThe first main electrode layerxe2x80x9d may mean either an anode electrode layer or a cathode electrode layer in the semiconductor diode or a thyristor. The thyristor is capable of including a gate turn-off (GTO) thyristor or a static induction thyristor (SI thyristor). If the third semiconductor region is n-type, then the first main electrode layer is a cathode electrode layer. xe2x80x9cThe second main electrode layerxe2x80x9d may mean either a cathode electrode layer or anode electrode layer in the semiconductor diode or thyristor, but not the above-mentioned first main electrode layer. If the second semiconductor region is assigned to be p-type, then the second main electrode layer is an anode electrode layer. As a result, the third semiconductor region serves as a xe2x80x9cfirst main electrode regionxe2x80x9d contacted to the first main electrode layer, and the second semiconductor region serves as a xe2x80x9csecond main electrode regionxe2x80x9d contacted to the second main electrode layer.
Moreover, the xe2x80x9cfirst main electrode layerxe2x80x9d may be either an emitter electrode layer or a collector electrode layer in a bipolar transistor (BJT) or an insulated-gate bipolar transistor (IGBT). A BJT may include an high frequency transistor such as a hetero-junction bipolar transistor (HBT), which operates in the microwave band, the millimeter-wave band or sub-millimeter-wave band. Moreover, the present invention may be applicable to an insulated-gate field effect transistor (IGFET) such as a metal-oxide-semiconductor field effect transistor (MOSFET), metal-oxide-semiconductor static induction transistor (MOSSIT), or high electron mobility transistor (HEMT). In this IGFET, the xe2x80x9cfirst main electrode layerxe2x80x9d, means either a source electrode layer or a drain electrode layer. In addition, in a BJT or an IGBT, the xe2x80x9csecond main electrode layerxe2x80x9d may mean either an emitter electrode layer or a collector electrode layer, but not the above-mentioned first main electrode layer; and in an IGFET, it may either mean a source electrode layer or drain electrode layer, but not the above-mentioned first main electrode layer. It is noted that in a BJT, an IGBT, an IGFET, or the like, it is also, of course, allowable to further add a control electrode layer for the base electrode layer, the gate electrode layer, or the like.
A second aspect of the present invention inheres in a method of manufacturing a semiconductor device encompassing, (a) forming a first semiconductor region by selectively doping first conductivity-type impurity elements through a first main surface of a semiconductor substrate to a predetermined diffusion depth; (b) forming a second semiconductor region, which is in contact with the first semiconductor region, by selectively doping the first conductivity-type impurity elements through second main surface of the semiconductor substrate to a predetermined diffusion depth; and (c) forming a third semiconductor region by doping second conductivity-type impurity elements having a conductivity type opposite that of the first conductivity type through the entire first main surface of the semiconductor substrate, and forming a p-n junction with the first semiconductor region. Here it is allowable for either the step of forming the first semiconductor region or the step of forming the second semiconductor region to be performed first. In addition, it is allowable for a diffusion window for selective diffusion to be opened in the first and second main surfaces, and diffusion be performed through both main surfaces simultaneously. Moreover, pre-deposition or an ion implantation process is performed first in the time sequence on either the first or second main surface side of the semiconductor substrate; however, the driving-in (annealing processing) process may be performed simultaneously, and the first and second semiconductor regions formed substantially simultaneously. The semiconductor substrate surrounding the first semiconductor region and the second semiconductor region and remaining as the base material corresponds to the fourth semiconductor region mentioned in the first aspect. As long as the impurity concentration is lower than the first or second semiconductor region, the semiconductor substrate may be either the first conductivity type, the second conductivity type, or even, an intrinsic semiconductor.
According to the method of manufacturing a semiconductor device according to the second aspect of the present invention, a first semiconductor region can be formed within the semiconductor substrate by selectively doping the first conductivity-type impurity elements through a first main surface of the semiconductor substrate. This first semiconductor region is formed with a higher impurity concentration than the fourth semiconductor region surrounding this first semiconductor region and second semiconductor region.
In the case where the semiconductor substrate is the first conductivity type, for example, two p-n junction interfaces may be implemented by bringing the high impurity concentration n-type first semiconductor region and the relatively low impurity concentration n-type semiconductor substrate (fourth semiconductor region) into contact with the p-type third semiconductor region. Therefore, after forming the first semiconductor region, it is possible for a breakdown to occur earlier in the p-n junction of the third semiconductor region, which is formed by doping the second conductivity-type impurity elements through the entire surface of the first main surface of the semiconductor substrate, and the first semiconductor region, than the p-n junction between the fourth semiconductor region and the third semiconductor region. As a result, the electric field at the sidewall (chip sidewall) of the semiconductor device is reduced, and a breakdown is made to occur in the junction interface within the semiconductor device allowing for stabilization of the device performance ascribable to the constant breakdown voltage.
In the case where the semiconductor substrate is the second conductivity type, the outside p-n junction interface is formed at the boundary of the second semiconductor region and the semiconductor substrate (fourth semiconductor region), and the outside p-n junction interface is not exposed to the outer surfaces of the semiconductor substrate (chip). Namely, in this case, the outside p-n junction interface is formed at the second main surface of the semiconductor substrate. More specifically, in this case, since the outside p-n junction interface is formed at the second main surface of the semiconductor substrate, there is no influence on it by changes in the surface state of the chip outer surface or surface damage. In particular, since the p-n junction is not exposed at the chip edge portion (chip outer surface), there is no detailed and complicated passivation architecture required for the chip outer surface. Moreover, it is possible to make it so that breakdown occurs earlier at the p-n junction at the boundary of the first semiconductor region and the third semiconductor region, than at the p-n junction exposed at the second main surface of the semiconductor substrate. As a result, the electric field of the second main surface side of the semiconductor substrate is reduced, and it is possible to make a breakdown occur at the junction interface within the semiconductor device, allowing stable device operation with a stabilized breakdown voltage.
In addition, by adjusting the impurity concentration of the first semiconductor region, it is possible to determine the electrical characteristics of the semiconductor device, and it is possible for the impurity concentration of the fourth semiconductor region to not have influence on the electrical characteristics of the semiconductor device. As a result, the semiconductor substrate can be utilized with the impurity concentration of the purchased specifications without requiring rigid setting of the impurity concentration. Therefore, it is possible to widen the range, from which the semiconductor substrate to be selected.
In addition, in the method of manufacturing a semiconductor device according to the second aspect of the present invention, by allowing for simultaneous performing of the thermal diffusion (driving-in) process of the first conductivity-type impurity elements for forming the second semiconductor region, and the thermal diffusion (driving-in) process of the second conductivity-type impurity elements for forming the third semiconductor region, the efficiency with which the semiconductor device is manufactured may be improved.
In the method of manufacturing a semiconductor device according to the second aspect of the present invention, it is preferable that there further include a process of dicing a plurality of semiconductor chips by cutting the semiconductor substrate along a plane substantially orthogonal with the p-n junction interface formed between the third semiconductor region and the first semiconductor region, and obtaining a plurality of semiconductor devices from the respective plurality of semiconductor chips. In this case, by adhering either one of the main surface sides of the semiconductor substrate to a synthetic resin sheet and then cutting the chips without cutting the adhered synthetic resin sheet, it is possible to store and transport each chip while still being adhered to the synthetic resin sheet. As a result, during product assembly, it becomes easier to handle the semiconductor device adhered to the synthetic resin sheet, for example, when loading into a jig such as the collet.
The third aspect of the present invention is a method of manufacturing a semiconductor device encompassing, (a) forming a first semiconductor region by selectively doping first conductivity-type impurity elements through a first main surface of a semiconductor substrate to a predetermined diffusion depth; (b) forming a second semiconductor region, which is in contact with the first semiconductor region, by selectively doping the first conductivity-type impurity elements through second main surface of the semiconductor substrate to a predetermined diffusion depth; and (c) forming a third semiconductor region by doping second conductivity-type impurity elements having a conductivity type opposite that of the first conductivity type through the entirety of the second main surface of the semiconductor substrate, and forming a p-n junction with the second semiconductor region. More specifically, the main surface on which the third semiconductor region is formed is the reverse of that of the method of manufacturing a semiconductor device according to the second aspect of the present invention. However, it makes no difference whether the step forming the first semiconductor region or the step forming the second semiconductor region is performed first. In addition, it is allowable for a diffusion window for selective diffusion to be opened in the first and second main surfaces of the semiconductor substrate, and diffusion be performed through both main surfaces simultaneously. Moreover, pre-deposition or an ion implantation process is performed first in the time sequence on either the first or second main surface side of the semiconductor substrate; however, the driving-in (annealing processing) process may be performed simultaneously, and the first and second semiconductor regions formed substantially simultaneously. Accordingly, the only problem left is which side to define as the xe2x80x9cfirst main surfacexe2x80x9d and the xe2x80x9csecond main surfacexe2x80x9d, which is substantially the same for the second aspect and the third aspect of the present invention. The semiconductor substrate surrounding the first semiconductor region and the second semiconductor region, and remaining as the base material corresponds to the fourth semiconductor region mentioned in the first aspect. As long as the impurity concentration is lower than the first or second semiconductor region, then the semiconductor substrate may be either the first conductivity type, the second conductivity type, or even, an intrinsic semiconductor.
The method of manufacturing a semiconductor device according to the third aspect of the present invention, as with the method of manufacturing a semiconductor device according to the second aspect, can form the second semiconductor region within the semiconductor substrate by selectively doping the first conductivity-type impurity elements through the second main surface of the semiconductor substrate. This second semiconductor region is formed with a higher impurity concentration than the fourth semiconductor region surrounding the first semiconductor region and the second semiconductor region.
When the semiconductor substrate is the first conductivity type, after forming the second semiconductor region, it is possible to have a breakdown occur at the p-n junction between the third semiconductor region and the second semiconductor region formed by doping the second conductivity-type impurity elements through the entire surface of the second main surface of the semiconductor substrate earlier than at the p-n junction between the fourth semiconductor region and the third semiconductor region. As a result, the electric field at the sidewall (chip sidewall) of the semiconductor substrate is reduced, and it is possible to make it so that a breakdown occurs at the junction interface within the semiconductor device, allowing stable device operation with a stabilized breakdown voltage.
When the semiconductor substrate is the second conductivity type, the outside p-n junction interface is formed at the boundary between the second semiconductor region and the semiconductor substrate (the fourth semiconductor region), and the outside p-n junction interface is not exposed at the outer surfaces of the semiconductor substrate (chip). More specifically, in this case, the outside p-n junction interface is formed at the second main surface of the semiconductor substrate. Namely, in this case, since the outside p-n junction interface is formed at the first main surface side of the semiconductor substrate, there is no influence on it from changes in the surface state of the chip outer surface or surface damage. In particular, since the p-n junction is not exposed at the edge portion (chip outer surface) of the chip, there is no detailed and complicated passivation architecture required for the chip outer surface. Moreover, a breakdown is allowed to occur in the p-n junction at the boundary of the first semiconductor region and the third semiconductor region, earlier than the p-n junction exposed at the first main surface side of the semiconductor substrate. As a result, the electric field at the second main surface side of the semiconductor substrate is reduced, and a breakdown is made to occur at the junction interface within the semiconductor device, allowing stable device operation with a stabilized breakdown voltage.
In addition, by adjusting the impurity concentration of the second semiconductor region, it is possible to determine the electrical characteristics of the semiconductor device, and remove the influence of the impurity concentration of the fourth semiconductor region on the electrical characteristics of the semiconductor device. As a result, the semiconductor substrate can be utilized with the impurity concentration of the purchased specifications without requiring rigid setting of the impurity concentration. In other words, it is possible to widen the range from which the semiconductor substrate may be selected.
In the method of manufacturing a semiconductor device according to the third aspect of the present invention, as with the method of manufacturing the semiconductor device according to the second aspect, it is preferable that there further include a process of dicing a plurality of semiconductor chips by cutting the semiconductor substrate along a plane substantially orthogonal with the p-n junction interface formed between the third semiconductor region and the first semiconductor region, and obtaining a plurality of semiconductor devices from the respective plurality of semiconductor chips. In this case, by adhering either one of the main surface sides of the semiconductor substrate to a synthetic resin sheet and then cutting the chips without cutting the adhered synthetic resin sheet, it is possible to store and transport each chip while being adhered to the synthetic resin sheet. As a result, during product assembly, it becomes easier to handle the semiconductor device adhered to the synthetic sheet, for example, when loading into a jig such as the collet.